%0 Conference Paper %1 conf/vlsid/RoyP07 %A Roy, Subir K. %A Parekhji, Rubin A. %B VLSI Design %D 2007 %I IEEE Computer Society %K dblp %P 364-372 %T Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2007.html#RoyP07 %@ 0-7695-2762-0

@inproceedings{conf/vlsid/RoyP07, added-at = {2023-03-24T00:00:00.000+0100}, author = {Roy, Subir K. and Parekhji, Rubin A.}, biburl = {https://www.bibsonomy.org/bibtex/2bc62c8de25e07a4826a291d44f7711de/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2007}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSID.2007.112}, interhash = {2e1f38abc3a953af0dc8bd8da1ffdbe9}, intrahash = {bc62c8de25e07a4826a291d44f7711de}, isbn = {0-7695-2762-0}, keywords = {dblp}, pages = {364-372}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:18:09.000+0200}, title = {Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2007.html#RoyP07}, year = 2007 }