%0 Conference Paper %1 conf/icetet/AswathaBS08 %A Aswatha, A. R. %A Basavaraju, T. G. %A Sarkar, Subir Kumar %B ICETET %D 2008 %I IEEE Computer Society %K dblp %P 414-417 %T Fast and Efficient On-Chip Interconnection Delay Modeling for High Speed VLSI Systems. %U http://dblp.uni-trier.de/db/conf/icetet/icetet2008.html#AswathaBS08 %@ 978-0-7695-3267-7

@inproceedings{conf/icetet/AswathaBS08, added-at = {2023-03-24T00:00:00.000+0100}, author = {Aswatha, A. R. and Basavaraju, T. G. and Sarkar, Subir Kumar}, biburl = {https://www.bibsonomy.org/bibtex/2bd3d036c96a56a220b6c6a450f40cd9f/dblp}, booktitle = {ICETET}, crossref = {conf/icetet/2008}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICETET.2008.87}, interhash = {ec0c440d19d85d0bc46d49f7a9ba9847}, intrahash = {bd3d036c96a56a220b6c6a450f40cd9f}, isbn = {978-0-7695-3267-7}, keywords = {dblp}, pages = {414-417}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T18:31:18.000+0200}, title = {Fast and Efficient On-Chip Interconnection Delay Modeling for High Speed VLSI Systems.}, url = {http://dblp.uni-trier.de/db/conf/icetet/icetet2008.html#AswathaBS08}, year = 2008 }