HSS16: A Hardware Simulator Software for Persona 16
K. Samsudin, A. Ramli, and I. Yusoff. Jurnal Teknologi D (Electronics, Control, Telecommunications and
Information Technology), (June 2002)
Abstract
Hardware Simulator Software for Pesona 16 (HSS16) is a simulated environment
of the Pesona-16 microprocessor for execution of the host-code to
enable parallel co-design and co-verification. The simulator core
is a typical Instruction Set Simulation (ISS) model, also called
Register Transfer Level (RTL) that incorporate an instruction simulation,
debugging facility and devices interfacing. The simulator is developed
with C and is capable of replacing the real hardware and are fully
modularised. Additional microprocessor architecture and devices can
be added without the need to rewrite the
simulator.
%0 Journal Article
%1 kmbs_utm_2002
%A K. Samsudin,
%A Ramli, A. R.
%A Yusoff, I. Mat
%D 2002
%I Universiti Teknologi Malaysia
%J Jurnal Teknologi D (Electronics, Control, Telecommunications and
Information Technology)
%K circuit, embedded
%N 36
%P 99-110
%T HSS16: A Hardware Simulator Software for Persona 16
%X Hardware Simulator Software for Pesona 16 (HSS16) is a simulated environment
of the Pesona-16 microprocessor for execution of the host-code to
enable parallel co-design and co-verification. The simulator core
is a typical Instruction Set Simulation (ISS) model, also called
Register Transfer Level (RTL) that incorporate an instruction simulation,
debugging facility and devices interfacing. The simulator is developed
with C and is capable of replacing the real hardware and are fully
modularised. Additional microprocessor architecture and devices can
be added without the need to rewrite the
simulator.
@article{kmbs_utm_2002,
abstract = {Hardware Simulator Software for Pesona 16 (HSS16) is a simulated environment
of the Pesona-16 microprocessor for execution of the host-code to
enable parallel co-design and co-verification. The simulator core
is a typical Instruction Set Simulation (ISS) model, also called
Register Transfer Level (RTL) that incorporate an instruction simulation,
debugging facility and devices interfacing. The simulator is developed
with C and is capable of replacing the real hardware and are fully
modularised. Additional microprocessor architecture and devices can
be added without the need to rewrite the
simulator.},
added-at = {2008-01-06T05:43:41.000+0100},
author = {{\bf K. Samsudin} and Ramli, A. R. and Yusoff, I. Mat},
biburl = {https://www.bibsonomy.org/bibtex/2be7230817813d3616b1cfe43ba6d416b/kmbs},
date-added = {2005-06-28 12:41:54 +0100},
date-modified = {2006-02-21 00:24:11 +0000},
description = {KMBS BibTex entry},
interhash = {727e4a9d313e027312299d41382b312f},
intrahash = {be7230817813d3616b1cfe43ba6d416b},
journal = {Jurnal Teknologi D (Electronics, Control, Telecommunications and
Information Technology)},
keywords = {circuit, embedded},
month = {June},
number = 36,
pages = {99-110},
publisher = {Universiti Teknologi Malaysia},
timestamp = {2008-01-06T05:43:42.000+0100},
title = {{HSS16}: A Hardware Simulator Software for {P}ersona 16},
year = 2002
}