%0 Journal Article %1 journals/tcasII/SuLWCLCHRHCMLSLCHLLHTC24 %A Su, Jian-Wei %A Lu, Pei-Jung %A Wu, Ping-Chun %A Chou, Yen-Chi %A Liu, Ta-Wei %A Chung, Yen-Lin %A Hung, Li-Yang %A Ren, Jin-Sheng %A Huang, Wei-Hsing %A Chien, Chih-Han %A Mei, Peng-I %A Li, Sih-Han %A Sheu, Shyh-Shyuan %A Lo, Wei-Chung %A Chang, Shih-Chieh %A Hong, Hao-Chiao %A Lo, Chung-Chuan %A Liu, Ren-Shuo %A Hsieh, Chih-Cheng %A Tang, Kea-Tiong %A Chang, Meng-Fan %D 2024 %J IEEE Trans. Circuits Syst. II Express Briefs %K dblp %N 4 %P 2304-2308 %T 8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips. %U http://dblp.uni-trier.de/db/journals/tcasII/tcasII71.html#SuLWCLCHRHCMLSLCHLLHTC24 %V 71

@article{journals/tcasII/SuLWCLCHRHCMLSLCHLLHTC24, added-at = {2024-04-15T00:00:00.000+0200}, author = {Su, Jian-Wei and Lu, Pei-Jung and Wu, Ping-Chun and Chou, Yen-Chi and Liu, Ta-Wei and Chung, Yen-Lin and Hung, Li-Yang and Ren, Jin-Sheng and Huang, Wei-Hsing and Chien, Chih-Han and Mei, Peng-I and Li, Sih-Han and Sheu, Shyh-Shyuan and Lo, Wei-Chung and Chang, Shih-Chieh and Hong, Hao-Chiao and Lo, Chung-Chuan and Liu, Ren-Shuo and Hsieh, Chih-Cheng and Tang, Kea-Tiong and Chang, Meng-Fan}, biburl = {https://www.bibsonomy.org/bibtex/2beeb61d88f8ef89110e1ae776a2154b6/dblp}, ee = {https://doi.org/10.1109/TCSII.2023.3331375}, interhash = {6afac4764ff932c066d5dff134ef5eba}, intrahash = {beeb61d88f8ef89110e1ae776a2154b6}, journal = {IEEE Trans. Circuits Syst. II Express Briefs}, keywords = {dblp}, month = {April}, number = 4, pages = {2304-2308}, timestamp = {2024-04-22T07:07:16.000+0200}, title = {8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips.}, url = {http://dblp.uni-trier.de/db/journals/tcasII/tcasII71.html#SuLWCLCHRHCMLSLCHLLHTC24}, volume = 71, year = 2024 }