%0 Conference Paper %1 conf/vlsid/RavikumarCV00 %A Ravikumar, C. P. %A Chandra, Gaurav %A Verma, Ashutosh %B VLSI Design %D 2000 %I IEEE Computer Society %K dblp %P 462-467 %T Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2000.html#RavikumarCV00 %@ 0-7695-0487-6

@inproceedings{conf/vlsid/RavikumarCV00, added-at = {2023-03-24T00:00:00.000+0100}, author = {Ravikumar, C. P. and Chandra, Gaurav and Verma, Ashutosh}, biburl = {https://www.bibsonomy.org/bibtex/2bf017e3386c3a44632d3c7171da1a481/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2000}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812650}, interhash = {9aef0a36ead3a9f71327b187010c3ba0}, intrahash = {bf017e3386c3a44632d3c7171da1a481}, isbn = {0-7695-0487-6}, keywords = {dblp}, pages = {462-467}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:19:01.000+0200}, title = {Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2000.html#RavikumarCV00}, year = 2000 }