%0 Generic %1 Byun2009227 %A Byun, J.-H.a %A Ravindran, A.a %A Mukherjee, A.a %A Joshi, B.a %A Chassin, D.b %C Napa, CA %D 2009 %J Proceedings - IEEE Symposium on Field Programmable Custom Computing Machines, FCCM 2009 %K Gridlab-D %P 227-230 %R 10.1109/FCCM.2009.23 %T Accelerating the gauss-seidel power flow solver on a high performance reconfigurable computer %U http://www.scopus.com/inward/record.url?eid=2-s2.0-74349126039&partnerID=40&md5=03bc2d6617af5e2e82d66bd26e457f0c %X The computationally intensive power flow problem determines the voltage magnitude and phase angle at each bus in a power system for hundreds of thousands of buses under balanced three-phase steady-state conditions. We report an FPGA acceleration of the Gauss-Seidel based power flow solver employed in the transmission module of the GridLAB-D power distribution simulator and analysis tool. The prototype hardware is implemented on an SGI Altix-RASC system equipped with a Xilinx Virtex-II 6000 FPGA. Due to capacity limitations of the FPGA, only the bus voltage calculations of the power network are implemented on hardware while the branch current calculations are implemented in software. For a 200,000 bus system, the bus voltage calculation on the FPGA achieves a 48x speed-up with PQ buses and a 62 times for PV over an equivalent sequential software implementation. The average overall speed up of the CPU-FPGA implementation with 100 iterations of the Gauss-Seidel power solver is 2.6x over a software implementation, with the branch calculations on the CPU accounting for 85% of the total execution time. The CPU-FPGA implementation also shows linear scaling with increase in the size of the input power network. Β© 2009 IEEE. %@ 9780769537160

@conference{Byun2009227, abbrev_source_title = {Proc. - IEEE Symp. Field Program. Custom Comput. Mach., FCCM}, abstract = {The computationally intensive power flow problem determines the voltage magnitude and phase angle at each bus in a power system for hundreds of thousands of buses under balanced three-phase steady-state conditions. We report an FPGA acceleration of the Gauss-Seidel based power flow solver employed in the transmission module of the GridLAB-D power distribution simulator and analysis tool. The prototype hardware is implemented on an SGI Altix-RASC system equipped with a Xilinx Virtex-II 6000 FPGA. Due to capacity limitations of the FPGA, only the bus voltage calculations of the power network are implemented on hardware while the branch current calculations are implemented in software. For a 200,000 bus system, the bus voltage calculation on the FPGA achieves a 48x speed-up with PQ buses and a 62 times for PV over an equivalent sequential software implementation. The average overall speed up of the CPU-FPGA implementation with 100 iterations of the Gauss-Seidel power solver is 2.6x over a software implementation, with the branch calculations on the CPU accounting for 85% of the total execution time. The CPU-FPGA implementation also shows linear scaling with increase in the size of the input power network. Β© 2009 IEEE.}, added-at = {2012-04-28T15:27:31.000+0200}, address = {Napa, CA}, affiliation = {Department of Electrical and Computer Engineering, University of North Carolina at Charlotte, Charlotte, NC 28223, United States; Pacific Northwest National Laboratory, Richland, WA 99352, United States}, art_number = {5290920}, author = {Byun, J.-H.a and Ravindran, A.a and Mukherjee, A.a and Joshi, B.a and Chassin, D.b}, author_keywords = {Bus voltage computations; FPGA; Gauss-Seidel; Power flow computing; Reconfigurable computing}, biburl = {https://www.bibsonomy.org/bibtex/2c266c7b5d179b420bde482fe1e51e4fe/adnasiak}, correspondence_address = {Byun, J.-H.; Department of Electrical and Computer Engineering, University of North Carolina at Charlotte, Charlotte, NC 28223, United States; email: jbyun1@uncc.edu}, description = {we need money}, document_type = {Conference Paper}, doi = {10.1109/FCCM.2009.23}, interhash = {282a324be4223595ae933ed63112c579}, intrahash = {c266c7b5d179b420bde482fe1e51e4fe}, isbn = {9780769537160}, journal = {Proceedings - IEEE Symposium on Field Programmable Custom Computing Machines, FCCM 2009}, keywords = {Gridlab-D}, language = {English}, note = {cited By (since 1996) 0; Conference of IEEE Symposium on Field Programmable Custom Computing Machines, FCCM 2009; Conference Date: 5 April 2009 through 7 April 2009; Conference Code: 78552}, pages = {227-230}, references = {Glover, J.D., Sarma, M.S., (2002) Power System Analysis and Design, , 3rd Edition. Brooks/Cole, Pacific Grove, California; Chassin, D.P., (2008) GridLAB-D Technical Support Document: Network Module Vesion 1.0, , http://www.gridlabd.org; Wang, X., Ziavras, S.G., Nwankpa, C., Johnson, J., Nagvajara, P., Parallel solution of Newton's power flow equations on configurable chips (2007) International Journal of Electrical Power & Energy Systems; P. Vachranukunkiet, Power Flow Computation Using Field Programmable Gate Arrays, Doctoral Thesis. UMI Order Number: AAI3261754., Drexel University, 2007Foertsch, J., Johnson, J., Nagvajara, P., Jacobi load flow accelerator using FPGA (2005) Proceedings of the 37th Annual North American Power Symposium; Chassin, D.P., Armstrong, P.R., Chavarria-Miranda, D.G., Guttromson, R.T., Gauss-Seidel Accelerated: Implementing Flow Solvers on Field Programmable Gate Arrays (2006) IEEE Power Engineering Society General Meeting}, source = {Scopus}, sponsors = {IEEE Computer Society Technical Committee on Computer; Architecture}, timestamp = {2012-04-28T15:41:55.000+0200}, title = {Accelerating the gauss-seidel power flow solver on a high performance reconfigurable computer}, url = {http://www.scopus.com/inward/record.url?eid=2-s2.0-74349126039&partnerID=40&md5=03bc2d6617af5e2e82d66bd26e457f0c}, year = 2009 }