%0 Journal Article %1 journals/jssc/LaiHH09 %A Lai, Ya-Chun %A Huang, Shi-Yu %A Hsu, Hsuan-Jung %D 2009 %J IEEE J. Solid State Circuits %K dblp %N 10 %P 2817-2823 %T Resilient Self-VDD-Tuning Scheme With Speed-Margining for Low-Power SRAM. %U http://dblp.uni-trier.de/db/journals/jssc/jssc44.html#LaiHH09 %V 44

@article{journals/jssc/LaiHH09, added-at = {2020-08-30T00:00:00.000+0200}, author = {Lai, Ya-Chun and Huang, Shi-Yu and Hsu, Hsuan-Jung}, biburl = {https://www.bibsonomy.org/bibtex/2c9e9fb55ba692ef46a3c3cb45fb35ffd/dblp}, ee = {https://doi.org/10.1109/JSSC.2009.2027543}, interhash = {2388e2ebd7028230b818ea0488ccc48c}, intrahash = {c9e9fb55ba692ef46a3c3cb45fb35ffd}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 10, pages = {2817-2823}, timestamp = {2020-08-31T11:44:18.000+0200}, title = {Resilient Self-VDD-Tuning Scheme With Speed-Margining for Low-Power SRAM.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc44.html#LaiHH09}, volume = 44, year = 2009 }