%0 Conference Paper %1 conf/vlsid/ChengCS07 %A Cheng, Fu-Chiung %A Chang, Shu-Ming %A Shieh, Chi-Huam %B VLSI Design %D 2007 %I IEEE Computer Society %K dblp %P 413-418 %T Detection and Generation of Self-Timed Pipelines from High Level Specifications. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2007.html#ChengCS07 %@ 0-7695-2762-0

@inproceedings{conf/vlsid/ChengCS07, added-at = {2023-03-24T00:00:00.000+0100}, author = {Cheng, Fu-Chiung and Chang, Shu-Ming and Shieh, Chi-Huam}, biburl = {https://www.bibsonomy.org/bibtex/2cc6ac784e656103cfd56b49b2c1eab34/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2007}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSID.2007.66}, interhash = {85d25d57264a80fffaf06fe94cf6ae6a}, intrahash = {cc6ac784e656103cfd56b49b2c1eab34}, isbn = {0-7695-2762-0}, keywords = {dblp}, pages = {413-418}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:18:09.000+0200}, title = {Detection and Generation of Self-Timed Pipelines from High Level Specifications.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2007.html#ChengCS07}, year = 2007 }