%0 Conference Paper %1 conf/itc/StadlerRKFFT99 %A Stadler, Manfred %A Röwer, Thomas %A Kaeslin, Hubert %A Felber, Norbert %A Fichtner, Wolfgang %A Thalmann, Markus %B ITC %D 1999 %I IEEE Computer Society %K dblp %P 414-420 %T Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor. %U http://dblp.uni-trier.de/db/conf/itc/itc1999.html#StadlerRKFFT99 %@ 0-7803-5753-1

@inproceedings{conf/itc/StadlerRKFFT99, added-at = {2023-03-23T00:00:00.000+0100}, author = {Stadler, Manfred and Röwer, Thomas and Kaeslin, Hubert and Felber, Norbert and Fichtner, Wolfgang and Thalmann, Markus}, biburl = {https://www.bibsonomy.org/bibtex/2d82da2b1c65b3b2342c7efc79bb78fcc/dblp}, booktitle = {ITC}, crossref = {conf/itc/1999}, ee = {https://doi.ieeecomputersociety.org/10.1109/TEST.1999.805763}, interhash = {61ae311f147d832926c3d7bd88b3e123}, intrahash = {d82da2b1c65b3b2342c7efc79bb78fcc}, isbn = {0-7803-5753-1}, keywords = {dblp}, pages = {414-420}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T19:53:23.000+0200}, title = {Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor.}, url = {http://dblp.uni-trier.de/db/conf/itc/itc1999.html#StadlerRKFFT99}, year = 1999 }