%0 Conference Paper %1 conf/socc/JiangSYS16 %A Jiang, Shixiong %A Saravanan, Vijayalakshmi %A Yan, Pengzhan %A Sridhar, Ramalingam %B SoCC %D 2016 %E Bhatia, Karan S. %E Alioto, Massimo %E Zhao, Danella %E Marshall, Andrew %E Sridhar, Ramalingam %I IEEE %K dblp %P 338-343 %T A fully parallel content addressable memory design using multi-bank structure. %U http://dblp.uni-trier.de/db/conf/socc/socc2016.html#JiangSYS16 %@ 978-1-5090-1367-8

@inproceedings{conf/socc/JiangSYS16, added-at = {2017-04-26T00:00:00.000+0200}, author = {Jiang, Shixiong and Saravanan, Vijayalakshmi and Yan, Pengzhan and Sridhar, Ramalingam}, biburl = {https://www.bibsonomy.org/bibtex/2d86c272c8b591e1948816f1864d2e112/dblp}, booktitle = {SoCC}, crossref = {conf/socc/2016}, editor = {Bhatia, Karan S. and Alioto, Massimo and Zhao, Danella and Marshall, Andrew and Sridhar, Ramalingam}, ee = {http://dx.doi.org/10.1109/SOCC.2016.7905506}, interhash = {7d77e5bc58873cb4b18a6385d1f3390c}, intrahash = {d86c272c8b591e1948816f1864d2e112}, isbn = {978-1-5090-1367-8}, keywords = {dblp}, pages = {338-343}, publisher = {IEEE}, timestamp = {2017-04-27T11:36:35.000+0200}, title = {A fully parallel content addressable memory design using multi-bank structure.}, url = {http://dblp.uni-trier.de/db/conf/socc/socc2016.html#JiangSYS16}, year = 2016 }