The complete architecture with the necessary blocks
and their internal structures are proposed in this paper. In
this algorithm the complete variable precision format is
utilized for the multiplication of the two numbers with a size
of nxn bits. The internal multiplier is choosen for m bit size
and is implemented using vedic-wallace structure for high
speed implementation. The architecture includes the
calculation of all the fields in the format for complete output.
The exponent of the final result is obtained by using carry
save adder for fast computations with less area utilization.
This multiplier uses the concept of MAC unit, giving rise to
more accurate results having a bits size of the final result will
be 2n2.
%0 Journal Article
%1 neelimakoppala2013efficient
%A Neelima Koppala, Rohit Sreerama
%A Paidi, Satish
%D 2013
%E ACEEE,
%J ACEEE Int. J. on Information Technology
%K Adder Carry MAC Precision Save Structure Variable Vedic Wallace
%N 1
%T An Area Efficient Vedic-Wallace based Variable
Precision Hardware Multiplier Algorithm
%U /brokenurl#doi.searchdl.org/01/IJIT/3/1/1113.pdf
%V 3
%X The complete architecture with the necessary blocks
and their internal structures are proposed in this paper. In
this algorithm the complete variable precision format is
utilized for the multiplication of the two numbers with a size
of nxn bits. The internal multiplier is choosen for m bit size
and is implemented using vedic-wallace structure for high
speed implementation. The architecture includes the
calculation of all the fields in the format for complete output.
The exponent of the final result is obtained by using carry
save adder for fast computations with less area utilization.
This multiplier uses the concept of MAC unit, giving rise to
more accurate results having a bits size of the final result will
be 2n2.
@article{neelimakoppala2013efficient,
abstract = {The complete architecture with the necessary blocks
and their internal structures are proposed in this paper. In
this algorithm the complete variable precision format is
utilized for the multiplication of the two numbers with a size
of nxn bits. The internal multiplier is choosen for m bit size
and is implemented using vedic-wallace structure for high
speed implementation. The architecture includes the
calculation of all the fields in the format for complete output.
The exponent of the final result is obtained by using carry
save adder for fast computations with less area utilization.
This multiplier uses the concept of MAC unit, giving rise to
more accurate results having a bits size of the final result will
be 2n2.
},
added-at = {2013-03-09T07:45:37.000+0100},
author = {Neelima Koppala, Rohit Sreerama and Paidi, Satish},
biburl = {https://www.bibsonomy.org/bibtex/2da6510426c82818ea8d3124fd895f5b5/ideseditor},
editor = {ACEEE},
interhash = {df17360991df7775ade99df622afb825},
intrahash = {da6510426c82818ea8d3124fd895f5b5},
journal = {ACEEE Int. J. on Information Technology},
keywords = {Adder Carry MAC Precision Save Structure Variable Vedic Wallace},
month = mar,
number = 1,
timestamp = {2013-03-09T07:45:37.000+0100},
title = {An Area Efficient Vedic-Wallace based Variable
Precision Hardware Multiplier Algorithm
},
url = {/brokenurl#doi.searchdl.org/01/IJIT/3/1/1113.pdf},
volume = 3,
year = 2013
}