%0 Conference Paper %1 conf/date/GerlachSRE17 %A Gerlach, Andreas %A Scheible, Jürgen %A Rosahl, Thoralf %A Eitrich, Frank-Thomas %B DATE %D 2017 %E Atienza, David %E Natale, Giorgio Di %I IEEE %K dblp %P 898-901 %T A generic topology selection method for analog circuits with embedded circuit sizing demonstrated on the OTA example. %U http://dblp.uni-trier.de/db/conf/date/date2017.html#GerlachSRE17 %@ 978-3-9815370-8-6

@inproceedings{conf/date/GerlachSRE17, added-at = {2017-08-14T00:00:00.000+0200}, author = {Gerlach, Andreas and Scheible, Jürgen and Rosahl, Thoralf and Eitrich, Frank-Thomas}, biburl = {https://www.bibsonomy.org/bibtex/2dd96580aaf92e13a3be097cb0d34c76c/dblp}, booktitle = {DATE}, crossref = {conf/date/2017}, editor = {Atienza, David and Natale, Giorgio Di}, ee = {http://dl.acm.org/citation.cfm?id=3130593}, interhash = {0e90bef3218644b2342baa0729b6e005}, intrahash = {dd96580aaf92e13a3be097cb0d34c76c}, isbn = {978-3-9815370-8-6}, keywords = {dblp}, pages = {898-901}, publisher = {IEEE}, timestamp = {2019-10-17T15:01:48.000+0200}, title = {A generic topology selection method for analog circuits with embedded circuit sizing demonstrated on the OTA example.}, url = {http://dblp.uni-trier.de/db/conf/date/date2017.html#GerlachSRE17}, year = 2017 }