%0 Journal Article %1 journals/ieicet/ShimanoMDA09 %A Shimano, Hiroki %A Morishita, Fukashi %A Dosaka, Katsumi %A Arimoto, Kazutami %D 2009 %J IEICE Trans. Electron. %K dblp %N 3 %P 356-363 %T On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet92c.html#ShimanoMDA09 %V 92-C

@article{journals/ieicet/ShimanoMDA09, added-at = {2023-06-26T00:00:00.000+0200}, author = {Shimano, Hiroki and Morishita, Fukashi and Dosaka, Katsumi and Arimoto, Kazutami}, biburl = {https://www.bibsonomy.org/bibtex/2dfecc17677dee9e3dfd070c969456413/dblp}, ee = {http://search.ieice.org/bin/summary.php?id=e92-c_3_356&category=C&year=2009&lang=E&abst=}, interhash = {6a5ece3d76cc27d1858f6acbfac8c5c9}, intrahash = {dfecc17677dee9e3dfd070c969456413}, journal = {IEICE Trans. Electron.}, keywords = {dblp}, number = 3, pages = {356-363}, timestamp = {2024-04-08T15:46:59.000+0200}, title = {On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet92c.html#ShimanoMDA09}, volume = {92-C}, year = 2009 }