%0 Conference Paper %1 conf/asicon/LiuXM11 %A Liu, Yucheng %A Xie, Jing %A Mao, Zhigang %B ASICON %D 2011 %I IEEE %K dblp %P 783-786 %T A reconfigurable linear array processor architecture for data parallel and computation intensive applications. %U http://dblp.uni-trier.de/db/conf/asicon/asicon2011.html#LiuXM11 %@ 978-1-61284-192-2

@inproceedings{conf/asicon/LiuXM11, added-at = {2020-02-08T00:00:00.000+0100}, author = {Liu, Yucheng and Xie, Jing and Mao, Zhigang}, biburl = {https://www.bibsonomy.org/bibtex/2e57bb0d06d7025fa6132538acadd4cb7/dblp}, booktitle = {ASICON}, crossref = {conf/asicon/2011}, ee = {https://doi.org/10.1109/ASICON.2011.6157322}, interhash = {971a99eb1d8f89836598f5761e913600}, intrahash = {e57bb0d06d7025fa6132538acadd4cb7}, isbn = {978-1-61284-192-2}, keywords = {dblp}, pages = {783-786}, publisher = {IEEE}, timestamp = {2020-02-11T11:46:01.000+0100}, title = {A reconfigurable linear array processor architecture for data parallel and computation intensive applications.}, url = {http://dblp.uni-trier.de/db/conf/asicon/asicon2011.html#LiuXM11}, year = 2011 }