%0 Journal Article %1 LiaYin16 %A Liang, Shuang %A Yin, Shouyi %A Liu, Leibo %A Guo, Yike %A Wei, Shaojun %D 2016 %J Computer Architecture Letters %K FPGA acceleration architecture hardware implementation map_reduce %N 2 %P 69-72 %T A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration. %U http://dblp.uni-trier.de/db/journals/cal/cal15.html#LiangYLGW16 %V 15

@article{LiaYin16, added-at = {2018-02-28T11:58:56.000+0100}, author = {Liang, Shuang and Yin, Shouyi and Liu, Leibo and Guo, Yike and Wei, Shaojun}, biburl = {https://www.bibsonomy.org/bibtex/2e7212d8ab48ffbdf0bd72da00455e114/loroch}, ee = {http://doi.ieeecomputersociety.org/10.1109/LCA.2015.2458318}, interhash = {d8360e221147e84fdf2b2127f2e0faed}, intrahash = {e7212d8ab48ffbdf0bd72da00455e114}, journal = {Computer Architecture Letters}, keywords = {FPGA acceleration architecture hardware implementation map_reduce}, number = 2, pages = {69-72}, timestamp = {2018-02-28T11:58:56.000+0100}, title = {A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration.}, url = {http://dblp.uni-trier.de/db/journals/cal/cal15.html#LiangYLGW16}, volume = 15, year = 2016 }