%0 Conference Paper %1 conf/dac/MenezesPP95 %A Menezes, Noel %A Pullela, Satyamurthy %A Pileggi, Lawrence T. %B DAC %D 1995 %E Preas, Bryan %I ACM Press %K dblp %P 690-695 %T Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. %U http://dblp.uni-trier.de/db/conf/dac/dac95.html#MenezesPP95 %@ 0-89791-725-1

@inproceedings{conf/dac/MenezesPP95, added-at = {2017-03-16T00:00:00.000+0100}, author = {Menezes, Noel and Pullela, Satyamurthy and Pileggi, Lawrence T.}, biburl = {https://www.bibsonomy.org/bibtex/2e8989b1e10f96f93dd2e5a163d9ee647/dblp}, booktitle = {DAC}, crossref = {conf/dac/1995}, editor = {Preas, Bryan}, ee = {http://doi.acm.org/10.1145/217474.217612}, interhash = {980aeab32e87d4847d65e49b37f33c9a}, intrahash = {e8989b1e10f96f93dd2e5a163d9ee647}, isbn = {0-89791-725-1}, keywords = {dblp}, pages = {690-695}, publisher = {ACM Press}, timestamp = {2017-03-17T11:39:46.000+0100}, title = {Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization.}, url = {http://dblp.uni-trier.de/db/conf/dac/dac95.html#MenezesPP95}, year = 1995 }