%0 Conference Paper %1 cong04application %A Cong, Jason %A Fan, Yiping %A Han, Guoling %A Zhang, Zhiru %B FPGA '04: Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays %C New York, NY, USA %D 2004 %I ACM %K ASIP Algorithms Compilation Design Experimentation Performance binate configurable covering mapping processor technology %P 183--189 %T Application-specific instruction generation for configurable processor architectures %U http://doi.acm.org/10.1145/968280.968307 %X Designing an application-specific embedded system in nanometer technologies has become more difficult than ever due to the rapid increase in design complexity and manufacturing cost. Efficiency and flexibility must be carefully balanced to meet different application requirements. The recently emerged configurable and extensible processor architectures offer a favorable tradeoff between efficiency and flexibility, and a promising way to minimize certain important metrics (e.g., execution time, code size, etc.) of the embedded processors. This paper addresses the problem of generating the application-specific instructions to improve the execution speed for configurable processors. A set of algorithms, including pattern generation, pattern selection, and application mapping, are proposed to efficiently utilize the instruction set extensibility of the target configurable processor. Applications of our approach to several real-life benchmarks on the Altera Nios processor show encouraging performance speedup (2.75X on average and up to 3.73X in some cases). %@ 1-58113-829-6

@inproceedings{cong04application, abstract = {Designing an application-specific embedded system in nanometer technologies has become more difficult than ever due to the rapid increase in design complexity and manufacturing cost. Efficiency and flexibility must be carefully balanced to meet different application requirements. The recently emerged configurable and extensible processor architectures offer a favorable tradeoff between efficiency and flexibility, and a promising way to minimize certain important metrics (e.g., execution time, code size, etc.) of the embedded processors. This paper addresses the problem of generating the application-specific instructions to improve the execution speed for configurable processors. A set of algorithms, including pattern generation, pattern selection, and application mapping, are proposed to efficiently utilize the instruction set extensibility of the target configurable processor. Applications of our approach to several real-life benchmarks on the Altera Nios processor show encouraging performance speedup (2.75X on average and up to 3.73X in some cases).}, added-at = {2008-01-19T11:45:36.000+0100}, address = {New York, NY, USA}, author = {Cong, Jason and Fan, Yiping and Han, Guoling and Zhang, Zhiru}, biburl = {https://www.bibsonomy.org/bibtex/2ed5beba834be0110fba32780f3878792/derkling}, booktitle = {FPGA '04: Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays}, description = {Application-specific instruction generation for configurable processor architectures}, interhash = {25824607467544d94d9bbd1f7843a23c}, intrahash = {ed5beba834be0110fba32780f3878792}, isbn = {1-58113-829-6}, keywords = {ASIP Algorithms Compilation Design Experimentation Performance binate configurable covering mapping processor technology}, location = {Monterey, California, USA}, pages = {183--189}, publisher = {ACM}, timestamp = {2008-01-19T11:45:36.000+0100}, title = {Application-specific instruction generation for configurable processor architectures}, url = {http://doi.acm.org/10.1145/968280.968307}, year = 2004 }