%0 Conference Paper %1 conf/vlsi-dat/DingHTFW12 %A Ding, Ruo-Ting %A Huang, Shi-Yu %A Tzeng, Chao-Wen %A Fang, Shan-Chien %A Weng, Chia-Chien %B VLSI-DAT %D 2012 %I IEEE %K dblp %P 1-4 %T Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property. %U http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2012.html#DingHTFW12 %@ 978-1-4577-2080-2

@inproceedings{conf/vlsi-dat/DingHTFW12, added-at = {2015-09-29T00:00:00.000+0200}, author = {Ding, Ruo-Ting and Huang, Shi-Yu and Tzeng, Chao-Wen and Fang, Shan-Chien and Weng, Chia-Chien}, biburl = {https://www.bibsonomy.org/bibtex/2ef45a0c10ba64c6b9ed84b78a62c6670/dblp}, booktitle = {VLSI-DAT}, crossref = {conf/vlsi-dat/2012}, ee = {http://dx.doi.org/10.1109/VLSI-DAT.2012.6212633}, interhash = {e6cf561f69b1d35204734f7b5faa2fcc}, intrahash = {ef45a0c10ba64c6b9ed84b78a62c6670}, isbn = {978-1-4577-2080-2}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2015-09-30T11:34:11.000+0200}, title = {Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property.}, url = {http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2012.html#DingHTFW12}, year = 2012 }