%0 Conference Paper %1 conf/isvlsi/LeshnerBYCPV10 %A Leshner, Samuel %A Berezowski, Krzysztof S. %A Yao, Xiaoyin %A Chalivendra, Gayathri %A Patel, Saurabh %A Vrudhula, Sarma B. K. %B ISVLSI %D 2010 %I IEEE Computer Society %K dblp %P 210-215 %T A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS. %U http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2010.html#LeshnerBYCPV10 %@ 978-0-7695-4076-4

@inproceedings{conf/isvlsi/LeshnerBYCPV10, added-at = {2023-03-24T00:00:00.000+0100}, author = {Leshner, Samuel and Berezowski, Krzysztof S. and Yao, Xiaoyin and Chalivendra, Gayathri and Patel, Saurabh and Vrudhula, Sarma B. K.}, biburl = {https://www.bibsonomy.org/bibtex/2f0be5f54071583c7bb1490c53395e17d/dblp}, booktitle = {ISVLSI}, crossref = {conf/isvlsi/2010}, ee = {https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2010.32}, interhash = {474dc36230d83caf9bea715fb0a6feb8}, intrahash = {f0be5f54071583c7bb1490c53395e17d}, isbn = {978-0-7695-4076-4}, keywords = {dblp}, pages = {210-215}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T11:07:55.000+0200}, title = {A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS.}, url = {http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2010.html#LeshnerBYCPV10}, year = 2010 }