%0 Conference Paper %1 conf/nanoarch/LiuCTZTW10 %A Liu, Bao %A Cao, Zhen %A Tao, Jun %A Zeng, Xuan %A Tang, Pushan %A Wong, H.-S. Philip %B NANOARCH %D 2010 %E Das, Shamik %E Bahar, Iris %E Niemier, Michael T. %I IEEE Computer Society %K dblp %P 77-81 %T Intel LVS logic as a combinational logic paradigm in CNT technology. %U http://dblp.uni-trier.de/db/conf/nanoarch/nanoarch2010.html#LiuCTZTW10 %@ 978-1-4244-8020-3

@inproceedings{conf/nanoarch/LiuCTZTW10, added-at = {2023-03-23T00:00:00.000+0100}, author = {Liu, Bao and Cao, Zhen and Tao, Jun and Zeng, Xuan and Tang, Pushan and Wong, H.-S. Philip}, biburl = {https://www.bibsonomy.org/bibtex/2f72ac4806b7b778ee2070a3927832e87/dblp}, booktitle = {NANOARCH}, crossref = {conf/nanoarch/2010}, editor = {Das, Shamik and Bahar, Iris and Niemier, Michael T.}, ee = {http://dl.acm.org/citation.cfm?id=1835979}, interhash = {b10476b0fcbb9690c288af02d93cb00e}, intrahash = {f72ac4806b7b778ee2070a3927832e87}, isbn = {978-1-4244-8020-3}, keywords = {dblp}, pages = {77-81}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T18:04:20.000+0200}, title = {Intel LVS logic as a combinational logic paradigm in CNT technology.}, url = {http://dblp.uni-trier.de/db/conf/nanoarch/nanoarch2010.html#LiuCTZTW10}, year = 2010 }