%0 Conference Paper %1 conf/hpcc/XuLLPT15 %A Xu, Thomas Canhao %A Leppänen, Ville %A Liljeberg, Pasi %A Plosila, Juha %A Tenhunen, Hannu %B HPCC/CSS/ICESS %D 2015 %I IEEE %K dblp %P 951-956 %T Trio: A Triple Class On-chip Network Design for Efficient Multicore Processors. %U http://dblp.uni-trier.de/db/conf/hpcc/hpcc2015.html#XuLLPT15 %@ 978-1-4799-8937-9

@inproceedings{conf/hpcc/XuLLPT15, added-at = {2022-04-09T00:00:00.000+0200}, author = {Xu, Thomas Canhao and Leppänen, Ville and Liljeberg, Pasi and Plosila, Juha and Tenhunen, Hannu}, biburl = {https://www.bibsonomy.org/bibtex/2fa6b5b19a0a3d0a6ce9bb481400fd036/dblp}, booktitle = {HPCC/CSS/ICESS}, crossref = {conf/hpcc/2015}, ee = {https://doi.org/10.1109/HPCC-CSS-ICESS.2015.44}, interhash = {fe9764f52550c65060aa5449263002fc}, intrahash = {fa6b5b19a0a3d0a6ce9bb481400fd036}, isbn = {978-1-4799-8937-9}, keywords = {dblp}, pages = {951-956}, publisher = {IEEE}, timestamp = {2024-04-10T03:21:15.000+0200}, title = {Trio: A Triple Class On-chip Network Design for Efficient Multicore Processors.}, url = {http://dblp.uni-trier.de/db/conf/hpcc/hpcc2015.html#XuLLPT15}, year = 2015 }