%0 Journal Article %1 journals/jssc/PanigadaG09 %A Panigada, Andrea %A Galton, Ian %D 2009 %J IEEE J. Solid State Circuits %K dblp %N 12 %P 3314-3328 %T A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction. %U http://dblp.uni-trier.de/db/journals/jssc/jssc44.html#PanigadaG09 %V 44

@article{journals/jssc/PanigadaG09, added-at = {2020-08-30T00:00:00.000+0200}, author = {Panigada, Andrea and Galton, Ian}, biburl = {https://www.bibsonomy.org/bibtex/2252fa7eeff56e694e9e1be0e8f0fd274/dblp}, ee = {https://doi.org/10.1109/JSSC.2009.2032637}, interhash = {3089a33fc51d8e126ad45ba8be39e1a8}, intrahash = {252fa7eeff56e694e9e1be0e8f0fd274}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 12, pages = {3314-3328}, timestamp = {2020-08-31T11:44:24.000+0200}, title = {A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc44.html#PanigadaG09}, volume = 44, year = 2009 }