%0 Journal Article %1 journals/jsa/HelbigSDDK93 %A Helbig, Johannes %A Schlör, Rainer %A Damm, Werner %A Döhmen, Gert %A Kelb, Peter %D 1993 %J Microprocessing and Microprogramming %K %N 1-5 %P 571-580 %T VHDL/S - integrating statecharts, timing diagrams, and VHDL. %U http://dblp.uni-trier.de/db/journals/jsa/jsa38.html#HelbigSDDK93 %V 38

@article{journals/jsa/HelbigSDDK93, added-at = {2023-12-12T20:32:28.000+0100}, author = {Helbig, Johannes and Schlör, Rainer and Damm, Werner and Döhmen, Gert and Kelb, Peter}, biburl = {https://www.bibsonomy.org/bibtex/2b4199e4e0d7a8661d55fe96106a2b2da/admin}, ee = {https://doi.org/10.1016/0165-6074(93)90197-S}, interhash = {30b10704e1b66e16cdf892b20dcddff3}, intrahash = {b4199e4e0d7a8661d55fe96106a2b2da}, journal = {Microprocessing and Microprogramming}, keywords = {}, number = {1-5}, pages = {571-580}, timestamp = {2023-12-12T20:32:28.000+0100}, title = {VHDL/S - integrating statecharts, timing diagrams, and VHDL.}, url = {http://dblp.uni-trier.de/db/journals/jsa/jsa38.html#HelbigSDDK93}, volume = 38, year = 1993 }