%0 Journal Article %1 journals/access/HuangMLWS21 %A Huang, Xianjin %A Mu, Feng %A Liu, Yixin %A Wu, Yuhan %A Sun, Hu %D 2021 %J IEEE Access %K dblp %P 86523-86534 %T Asynchronous Gate Signal Driving Method for Reducing Current Imbalance of Paralleled IGBT Modules Caused by Driving Circuit Parameter Difference. %U http://dblp.uni-trier.de/db/journals/access/access9.html#HuangMLWS21 %V 9

@article{journals/access/HuangMLWS21, added-at = {2023-02-06T00:00:00.000+0100}, author = {Huang, Xianjin and Mu, Feng and Liu, Yixin and Wu, Yuhan and Sun, Hu}, biburl = {https://www.bibsonomy.org/bibtex/2f0ee9458b5f7d859fd678d948a74abe5/dblp}, ee = {https://doi.org/10.1109/ACCESS.2021.3089495}, interhash = {314596c0ba3c86560e95918ec2023401}, intrahash = {f0ee9458b5f7d859fd678d948a74abe5}, journal = {IEEE Access}, keywords = {dblp}, pages = {86523-86534}, timestamp = {2024-04-08T14:09:55.000+0200}, title = {Asynchronous Gate Signal Driving Method for Reducing Current Imbalance of Paralleled IGBT Modules Caused by Driving Circuit Parameter Difference.}, url = {http://dblp.uni-trier.de/db/journals/access/access9.html#HuangMLWS21}, volume = 9, year = 2021 }