%0 Conference Paper %1 conf/hotchips/TurullolsS12 %A Turullols, Sebastian %A Sivaramakrishnan, Ram %B Hot Chips Symposium %D 2012 %I IEEE %K dblp %P 1-37 %T SPARC T5: 16-core CMT processor with glueless 1-hop scaling to 8-sockets. %U http://dblp.uni-trier.de/db/conf/hotchips/hotchips2012.html#TurullolsS12 %@ 978-1-4673-8879-5

@inproceedings{conf/hotchips/TurullolsS12, added-at = {2023-03-24T00:00:00.000+0100}, author = {Turullols, Sebastian and Sivaramakrishnan, Ram}, biburl = {https://www.bibsonomy.org/bibtex/266883c4ccb86a9bed3585efbc715e990/dblp}, booktitle = {Hot Chips Symposium}, crossref = {conf/hotchips/2012}, ee = {https://doi.ieeecomputersociety.org/10.1109/HOTCHIPS.2012.7476504}, interhash = {33849cbdad548e8a49027afebfb2db26}, intrahash = {66883c4ccb86a9bed3585efbc715e990}, isbn = {978-1-4673-8879-5}, keywords = {dblp}, pages = {1-37}, publisher = {IEEE}, timestamp = {2024-04-09T09:48:49.000+0200}, title = {SPARC T5: 16-core CMT processor with glueless 1-hop scaling to 8-sockets.}, url = {http://dblp.uni-trier.de/db/conf/hotchips/hotchips2012.html#TurullolsS12}, year = 2012 }