%0 Conference Paper %1 conf/vlsid/LuA08 %A Lu, Yuanlin %A Agrawal, Vishwani D. %B VLSI Design %D 2008 %I IEEE Computer Society %K dblp %P 527-532 %T Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2008.html#LuA08 %@ 0-7695-3083-4

@inproceedings{conf/vlsid/LuA08, added-at = {2023-03-24T00:00:00.000+0100}, author = {Lu, Yuanlin and Agrawal, Vishwani D.}, biburl = {https://www.bibsonomy.org/bibtex/270bb1aa05fdcd6de7e96c335d6ee62d2/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2008}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSI.2008.29}, interhash = {33e243d4ba202db0292b82ff26515cd2}, intrahash = {70bb1aa05fdcd6de7e96c335d6ee62d2}, isbn = {0-7695-3083-4}, keywords = {dblp}, pages = {527-532}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:19:22.000+0200}, title = {Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2008.html#LuA08}, year = 2008 }