%0 Journal Article %1 noauthororeditor %A Chauhan, Sarita %A Singh, Bahadur %A Vishnoi, Bhajanlal %A Saini, Subhash %A Kala, Vikas %D 2015 %E Kumar, Dr. Shiv %J International Journal of Innovative Science and Modern Engineering (IJISME) %K %N 5 %P 32-39 %T Emulation of Artificial Neural Network on an FPGA-based Accelerator using CYCLONE II %U https://www.ijisme.org/wp-content/uploads/papers/v3i5/E0842043515.pdf %V 3 %X Analog VLSI circuits are being used successfully to implement Artificial Neural Networks (ANNs). These analog circuits exhibit nonlinear transfer function characteristics and suffer from device mismatches, degrading network performance. Because of the high cost involved with analog VLSI production, it is beneficial to predict implementation performance during design. We used hardware timemultiplexing to scale network size and maximize hardware usage. An on-chip CPU controls the data flow through various memory systems to allow for large test sequences.We show that Block-RAM availability is the main implementation bottleneck and that a trade-off arises between emulation speed and hardware resources. However, we can emulate large amounts of synapses on an FPGA with limited resources. We have obtained a speedup of 30.5 times with respect to an optimized software implementation on a desktop computer.

@article{noauthororeditor, abstract = {Analog VLSI circuits are being used successfully to implement Artificial Neural Networks (ANNs). These analog circuits exhibit nonlinear transfer function characteristics and suffer from device mismatches, degrading network performance. Because of the high cost involved with analog VLSI production, it is beneficial to predict implementation performance during design. We used hardware timemultiplexing to scale network size and maximize hardware usage. An on-chip CPU controls the data flow through various memory systems to allow for large test sequences.We show that Block-RAM availability is the main implementation bottleneck and that a trade-off arises between emulation speed and hardware resources. However, we can emulate large amounts of synapses on an FPGA with limited resources. We have obtained a speedup of 30.5 times with respect to an optimized software implementation on a desktop computer.}, added-at = {2021-09-20T13:30:27.000+0200}, author = {Chauhan, Sarita and Singh, Bahadur and Vishnoi, Bhajanlal and Saini, Subhash and Kala, Vikas}, biburl = {https://www.bibsonomy.org/bibtex/2b93b25b3989f45cd0c0dc2e409944113/ijisme_beiesp}, editor = {Kumar, Dr. Shiv}, interhash = {33edc0e8f1edd110f101f31c301b7134}, intrahash = {b93b25b3989f45cd0c0dc2e409944113}, issn = {2319-6386}, journal = {International Journal of Innovative Science and Modern Engineering (IJISME)}, keywords = {}, language = {En}, month = {April}, number = 5, pages = {32-39}, timestamp = {2021-09-20T13:30:26.000+0200}, title = {Emulation of Artificial Neural Network on an FPGA-based Accelerator using CYCLONE II}, url = {https://www.ijisme.org/wp-content/uploads/papers/v3i5/E0842043515.pdf}, volume = 3, year = 2015 }