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%0 Conference Paper
%1 conf/itc/SakashitaOSSHTKKYA96
%A Sakashita, Narumi
%A Okuda, Fumihiro
%A Shimomura, Ken'ichi
%A Shimano, Hiroki
%A Hamada, Mitsuhiro
%A Tada, Tetsuo
%A Komori, Shinji
%A Kyuma, Kazuo
%A Yasuoka, Akihiko
%A Abe, Haruhiko
%B ITC
%D 1996
%I IEEE Computer Society
%K dblp
%P 319-324
%T A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM.
%U http://dblp.uni-trier.de/db/conf/itc/itc1996.html#SakashitaOSSHTKKYA96
%@ 0-7803-3541-4
@inproceedings{conf/itc/SakashitaOSSHTKKYA96,
added-at = {2023-03-23T00:00:00.000+0100},
author = {Sakashita, Narumi and Okuda, Fumihiro and Shimomura, Ken'ichi and Shimano, Hiroki and Hamada, Mitsuhiro and Tada, Tetsuo and Komori, Shinji and Kyuma, Kazuo and Yasuoka, Akihiko and Abe, Haruhiko},
biburl = {https://www.bibsonomy.org/bibtex/29cfeabda6421807d151dbc7cb5a214a3/dblp},
booktitle = {ITC},
crossref = {conf/itc/1996},
ee = {https://doi.ieeecomputersociety.org/10.1109/TEST.1996.556977},
interhash = {357aeba1343e78475f67f6f53f179dfc},
intrahash = {9cfeabda6421807d151dbc7cb5a214a3},
isbn = {0-7803-3541-4},
keywords = {dblp},
pages = {319-324},
publisher = {IEEE Computer Society},
timestamp = {2024-04-10T19:52:20.000+0200},
title = {A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM.},
url = {http://dblp.uni-trier.de/db/conf/itc/itc1996.html#SakashitaOSSHTKKYA96},
year = 1996
}