%0 Conference Paper %1 conf/ipccc/XuXWP14 %A Xu, Jinbo %A Xu, Weixia %A Wang, Kefei %A Pang, Zhengbin %B IPCCC %D 2014 %I IEEE Computer Society %K dblp %P 1-2 %T Low-latency last-level cache structure based on grouped cores in Chip Multi-Processor. %U http://dblp.uni-trier.de/db/conf/ipccc/ipccc2014.html#XuXWP14 %@ 978-1-4799-7575-4

@inproceedings{conf/ipccc/XuXWP14, added-at = {2023-03-24T00:00:00.000+0100}, author = {Xu, Jinbo and Xu, Weixia and Wang, Kefei and Pang, Zhengbin}, biburl = {https://www.bibsonomy.org/bibtex/26a9fe95f987ebe199edbc7b580b8749a/dblp}, booktitle = {IPCCC}, crossref = {conf/ipccc/2014}, ee = {https://doi.ieeecomputersociety.org/10.1109/PCCC.2014.7017021}, interhash = {391771f1e83049677e0bc70c92d14887}, intrahash = {6a9fe95f987ebe199edbc7b580b8749a}, isbn = {978-1-4799-7575-4}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:46:07.000+0200}, title = {Low-latency last-level cache structure based on grouped cores in Chip Multi-Processor.}, url = {http://dblp.uni-trier.de/db/conf/ipccc/ipccc2014.html#XuXWP14}, year = 2014 }