%0 Journal Article %1 journals/tc/HosseinabadySLN08 %A Hosseinabady, Mohammad %A Sharifi, Shervin %A Lombardi, Fabrizio %A Navabi, Zainalabedin %D 2008 %J IEEE Trans. Computers %K dblp %N 3 %P 316-328 %T A Selective Trigger Scan Architecture for VLSI Testing. %U http://dblp.uni-trier.de/db/journals/tc/tc57.html#HosseinabadySLN08 %V 57

@article{journals/tc/HosseinabadySLN08, added-at = {2024-02-05T00:00:00.000+0100}, author = {Hosseinabady, Mohammad and Sharifi, Shervin and Lombardi, Fabrizio and Navabi, Zainalabedin}, biburl = {https://www.bibsonomy.org/bibtex/2cbaeb6c79a729e51bfc3b8d31ff0e62e/dblp}, ee = {http://doi.ieeecomputersociety.org/10.1109/TC.2007.70806}, interhash = {3c537179e97b8605ae34b1ad36d52f8a}, intrahash = {cbaeb6c79a729e51bfc3b8d31ff0e62e}, journal = {IEEE Trans. Computers}, keywords = {dblp}, number = 3, pages = {316-328}, timestamp = {2024-04-08T18:29:04.000+0200}, title = {A Selective Trigger Scan Architecture for VLSI Testing.}, url = {http://dblp.uni-trier.de/db/journals/tc/tc57.html#HosseinabadySLN08}, volume = 57, year = 2008 }