%0 Conference Paper %1 conf/fpl/CampregherCCV05 %A Campregher, Nicola %A Cheung, Peter Y. K. %A Constantinides, George A. %A Vasilko, Milan %B FPL %D 2005 %E Rissa, Tero %E Wilton, Steven J. E. %E Leong, Philip Heng Wai %I IEEE %K %P 409-414 %T Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2005.html#CampregherCCV05 %@ 0-7803-9362-7

@inproceedings{conf/fpl/CampregherCCV05, added-at = {2023-12-12T21:30:19.000+0100}, author = {Campregher, Nicola and Cheung, Peter Y. K. and Constantinides, George A. and Vasilko, Milan}, biburl = {https://www.bibsonomy.org/bibtex/20630306cab68fcbcf218b0adab7541a7/admin}, booktitle = {FPL}, crossref = {conf/fpl/2005}, editor = {Rissa, Tero and Wilton, Steven J. E. and Leong, Philip Heng Wai}, ee = {http://doi.ieeecomputersociety.org/10.1109/FPL.2005.1515756}, interhash = {3f2aa454cca0ee595833eb5dd8d445dd}, intrahash = {0630306cab68fcbcf218b0adab7541a7}, isbn = {0-7803-9362-7}, keywords = {}, pages = {409-414}, publisher = {IEEE}, timestamp = {2023-12-12T21:30:19.000+0100}, title = {Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2005.html#CampregherCCV05}, year = 2005 }