%0 Conference Paper %1 conf/vlsid/VenkataramaniA13 %A Venkataramani, Praveen %A Agrawal, Vishwani D. %B VLSI Design %D 2013 %I IEEE Computer Society %K dblp %P 273-278 %T Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2013.html#VenkataramaniA13 %@ 978-1-4673-4639-9

@inproceedings{conf/vlsid/VenkataramaniA13, added-at = {2023-03-24T00:00:00.000+0100}, author = {Venkataramani, Praveen and Agrawal, Vishwani D.}, biburl = {https://www.bibsonomy.org/bibtex/294c67b7564c8bafa114c26f7463577ec/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2013}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSID.2013.200}, interhash = {40b01a10b18616fd154c0eb0784bc3d2}, intrahash = {94c67b7564c8bafa114c26f7463577ec}, isbn = {978-1-4673-4639-9}, keywords = {dblp}, pages = {273-278}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:08:28.000+0200}, title = {Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2013.html#VenkataramaniA13}, year = 2013 }