%0 Conference Paper %1 conf/vlsid/ChenPB02 %A Chen, Wei %A Pedram, Massoud %A Buch, Premal %B ASP-DAC/VLSI Design %D 2002 %I IEEE Computer Society %K dblp %P 381-386 %T Buffered Routing Tree Construction under Buffer Placement Blockages. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2002.html#ChenPB02 %@ 0-7695-1299-2

@inproceedings{conf/vlsid/ChenPB02, added-at = {2022-11-14T00:00:00.000+0100}, author = {Chen, Wei and Pedram, Massoud and Buch, Premal}, biburl = {https://www.bibsonomy.org/bibtex/24900f1dbe79850a416329f5f34e14446/dblp}, booktitle = {ASP-DAC/VLSI Design}, crossref = {conf/vlsid/2002}, ee = {https://dl.acm.org/doi/10.5555/832284.835458}, interhash = {452dc40ed8d761d2f9c78574266ea7c8}, intrahash = {4900f1dbe79850a416329f5f34e14446}, isbn = {0-7695-1299-2}, keywords = {dblp}, pages = {381-386}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T01:05:13.000+0200}, title = {Buffered Routing Tree Construction under Buffer Placement Blockages.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2002.html#ChenPB02}, year = 2002 }