%0 Journal Article %1 journals/jssc/JeonLLJMCP04 %A Jeon, Young-Jin %A Lee, Joong-Ho %A Lee, Hyun-Chul %A Jin, Kyo-Won %A Min, Kyeong-Sik %A Chung, Jin-Yong %A Park, Hong-June %D 2004 %J IEEE J. Solid State Circuits %K dblp %N 11 %P 2087-2092 %T A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs. %U http://dblp.uni-trier.de/db/journals/jssc/jssc39.html#JeonLLJMCP04 %V 39

@article{journals/jssc/JeonLLJMCP04, added-at = {2022-04-22T00:00:00.000+0200}, author = {Jeon, Young-Jin and Lee, Joong-Ho and Lee, Hyun-Chul and Jin, Kyo-Won and Min, Kyeong-Sik and Chung, Jin-Yong and Park, Hong-June}, biburl = {https://www.bibsonomy.org/bibtex/2effde40a621d9f4d4059f8b7c05a1bc5/dblp}, ee = {https://doi.org/10.1109/JSSC.2004.835809}, interhash = {45ec071297a1403c037bf8d14737e53d}, intrahash = {effde40a621d9f4d4059f8b7c05a1bc5}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 11, pages = {2087-2092}, timestamp = {2024-04-08T10:43:12.000+0200}, title = {A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc39.html#JeonLLJMCP04}, volume = 39, year = 2004 }