Abstract
The continued speed improvement of serial links
and appearance of new communication technologies, such as
ultra-wideband (UWB), have introduced increasing demands
on the speed and power specifications of high-speed low-to-
medium resolution analog-to-digital converters (ADCs).This
paper presents the design of high speed and ultra low power
comparator of a 4-bit ADC. The comparator used is Threshold
Inverter Quantization (TIQ) consuming less than 145μW power
with the input frequency of 1GHz and is designed using
standard CMOS (Complementary Metal Oxide
Semiconductor) technology. The power supply voltage is 0.7V
minimum which makes this design adaptable to wide variety
of System-on-Chip (SoC) applications. The complete design of
ADC is clockless which reduces the electromagnetic
interference and gives better modularity. The ADC is targeted
for 45nm as it was the mainstream CMOS technology, at the
beginning of this research. However, the circuit should be
portable to smaller feature size CMOS technologies with lower
supply voltages.
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