%0 Conference Paper %1 conf/isvlsi/NetoTAAG19 %A Neto, Walter Lau %A Tang, Xifan %A Austin, Max %A Amarù, Luca G. %A Gaillardon, Pierre-Emmanuel %B ISVLSI %D 2019 %I IEEE %K dblp %P 224-229 %T Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs. %U http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2019.html#NetoTAAG19 %@ 978-1-7281-3391-1

@inproceedings{conf/isvlsi/NetoTAAG19, added-at = {2019-09-24T00:00:00.000+0200}, author = {Neto, Walter Lau and Tang, Xifan and Austin, Max and Amarù, Luca G. and Gaillardon, Pierre-Emmanuel}, biburl = {https://www.bibsonomy.org/bibtex/2cf42e406e35c760fa3d5d199ffacd6db/dblp}, booktitle = {ISVLSI}, crossref = {conf/isvlsi/2019}, ee = {https://doi.org/10.1109/ISVLSI.2019.00049}, interhash = {47116121643511f39614bdd887f6f83d}, intrahash = {cf42e406e35c760fa3d5d199ffacd6db}, isbn = {978-1-7281-3391-1}, keywords = {dblp}, pages = {224-229}, publisher = {IEEE}, timestamp = {2019-10-17T13:45:19.000+0200}, title = {Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs.}, url = {http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2019.html#NetoTAAG19}, year = 2019 }