%0 Conference Paper %1 conf/fpga/MaCVS17 %A Ma, Yufei %A Cao, Yu %A Vrudhula, Sarma B. K. %A sun Seo, Jae %B FPGA %D 2017 %E Greene, Jonathan W. %E Anderson, Jason Helge %I ACM %K dblp %P 45-54 %T Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks. %U http://dblp.uni-trier.de/db/conf/fpga/fpga2017.html#MaCVS17 %@ 978-1-4503-4354-1

@inproceedings{conf/fpga/MaCVS17, added-at = {2022-08-16T00:00:00.000+0200}, author = {Ma, Yufei and Cao, Yu and Vrudhula, Sarma B. K. and sun Seo, Jae}, biburl = {https://www.bibsonomy.org/bibtex/26b7f38de618d80780bd910543fcfba77/dblp}, booktitle = {FPGA}, crossref = {conf/fpga/2017}, editor = {Greene, Jonathan W. and Anderson, Jason Helge}, ee = {http://dl.acm.org/citation.cfm?id=3021736}, interhash = {4b815ccca57f915007b53c03a662b60a}, intrahash = {6b7f38de618d80780bd910543fcfba77}, isbn = {978-1-4503-4354-1}, keywords = {dblp}, pages = {45-54}, publisher = {ACM}, timestamp = {2024-04-10T11:24:20.000+0200}, title = {Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks.}, url = {http://dblp.uni-trier.de/db/conf/fpga/fpga2017.html#MaCVS17}, year = 2017 }