%0 Journal Article %1 journals/tcad/AroraRSR96 %A Arora, Narain D. %A Raol, Kartik V. %A Schumann, Reinhard %A Richardson, Llanda M. %D 1996 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 1 %P 58-67 %T Modeling and extraction of interconnect capacitances for multilayer VLSI circuits. %U http://dblp.uni-trier.de/db/journals/tcad/tcad15.html#AroraRSR96 %V 15

@article{journals/tcad/AroraRSR96, added-at = {2020-09-24T00:00:00.000+0200}, author = {Arora, Narain D. and Raol, Kartik V. and Schumann, Reinhard and Richardson, Llanda M.}, biburl = {https://www.bibsonomy.org/bibtex/2e4e56c9141f8adbf39cb902eee68b4a6/dblp}, ee = {https://doi.org/10.1109/43.486272}, interhash = {4f383f100f66f9c3533bdd9d142b5fac}, intrahash = {e4e56c9141f8adbf39cb902eee68b4a6}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 1, pages = {58-67}, timestamp = {2020-09-25T11:49:22.000+0200}, title = {Modeling and extraction of interconnect capacitances for multilayer VLSI circuits.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad15.html#AroraRSR96}, volume = 15, year = 1996 }