%0 Conference Paper %1 conf/apccas/PyunKC16 %A Pyun, Ki-Hyun %A Kwon, Dae Hyun %A Choi, Woo-Young %B APCCAS %D 2016 %I IEEE %K %P 327-329 %T A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector. %U http://dblp.uni-trier.de/db/conf/apccas/apccas2016.html#PyunKC16 %@ 978-1-5090-1570-2

@inproceedings{conf/apccas/PyunKC16, added-at = {2023-12-12T22:53:16.000+0100}, author = {Pyun, Ki-Hyun and Kwon, Dae Hyun and Choi, Woo-Young}, biburl = {https://www.bibsonomy.org/bibtex/23b5f78176bf95edbc5dcfc1402f7ef46/admin}, booktitle = {APCCAS}, crossref = {conf/apccas/2016}, ee = {http://dx.doi.org/10.1109/APCCAS.2016.7803966}, interhash = {4f5159a5cac75445b11bcb85ceea3d5e}, intrahash = {3b5f78176bf95edbc5dcfc1402f7ef46}, isbn = {978-1-5090-1570-2}, keywords = {}, pages = {327-329}, publisher = {IEEE}, timestamp = {2023-12-12T22:53:16.000+0100}, title = {A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector.}, url = {http://dblp.uni-trier.de/db/conf/apccas/apccas2016.html#PyunKC16}, year = 2016 }