%0 Conference Paper %1 conf/aspdac/FalkensternXCW10 %A Falkenstern, Paul %A Xie, Yuan %A Chang, Yao-Wen %A Wang, Yu %B ASP-DAC %D 2010 %I IEEE %K dblp %P 169-174 %T Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2010.html#FalkensternXCW10 %@ 978-1-60558-837-7

@inproceedings{conf/aspdac/FalkensternXCW10, added-at = {2017-06-01T00:00:00.000+0200}, author = {Falkenstern, Paul and Xie, Yuan and Chang, Yao-Wen and Wang, Yu}, biburl = {https://www.bibsonomy.org/bibtex/2ab3057570602b951e24eb34dd19375cd/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2010}, ee = {http://dl.acm.org/citation.cfm?id=1899759}, interhash = {5075aefc8a56d90045ac94a1038055b6}, intrahash = {ab3057570602b951e24eb34dd19375cd}, isbn = {978-1-60558-837-7}, keywords = {dblp}, pages = {169-174}, publisher = {IEEE}, timestamp = {2019-10-17T16:46:10.000+0200}, title = {Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2010.html#FalkensternXCW10}, year = 2010 }