Abstract
Ultra-Wideband (UWB) communication systems are
currently the focus of research and development in wireless
personal area networks (WPANs). These systems are capable
of transferring data from a rate of 110Mbps to 480Mbps in
realistic multipath environment. They consume very little
power and silicon area. In such systems, synchronization plays
very critical role to ensure correct and reliable system
operation. Improper synchronization can introduce timing
errors during transmission that can be eliminated using a
device called scrambler. In this paper, the scrambler for UWB
communication systems has been modeled and simulated using
Matlab and Xilinx’s System Generator for DSP (Digital Signal
Processing). Implementation of the scrambler has also been
done on Spartan 3E FPGA (Field Programmable Gate Array)
chip using Xilinx’s ISE Design Suite and results are compared.
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