%0 Journal Article %1 journals/jssc/ChenCCPWLLY09 %A Chen, Yen-Huei %A Chan, Gary %A Chou, Shao-Yu %A Pan, Hsien-Yu %A Wu, Jui-Jen %A Lee, Robin %A Liao, Hung-Jen %A Yamauchi, Hiroyuki %D 2009 %J IEEE J. Solid State Circuits %K dblp %N 4 %P 1209-1215 %T A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs. %U http://dblp.uni-trier.de/db/journals/jssc/jssc44.html#ChenCCPWLLY09 %V 44

@article{journals/jssc/ChenCCPWLLY09, added-at = {2024-02-05T00:00:00.000+0100}, author = {Chen, Yen-Huei and Chan, Gary and Chou, Shao-Yu and Pan, Hsien-Yu and Wu, Jui-Jen and Lee, Robin and Liao, Hung-Jen and Yamauchi, Hiroyuki}, biburl = {https://www.bibsonomy.org/bibtex/24b07188f918f06f9d25e839bd5cbf677/dblp}, ee = {https://www.wikidata.org/entity/Q122914542}, interhash = {532bc6112403c95fcfa154edbe73b268}, intrahash = {4b07188f918f06f9d25e839bd5cbf677}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 4, pages = {1209-1215}, timestamp = {2024-04-08T10:44:19.000+0200}, title = {A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc44.html#ChenCCPWLLY09}, volume = 44, year = 2009 }