Inproceedings,
10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter.
D. Xu, Z. Liu, Y. Kuai, H. Huang, Y. Zhang, Z. Sun, B. Liu, W. Wang, Y. Xiong, J. Qiu, W. Madany, Y. Zhang, A. Fadila, A. Shirane, and K. Okada.ISSCC, page 192-194. IEEE, (2024)
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- BibTeX key
- conf/isscc/XuLKHZSLWXQMZFSO24
- entry type
- inproceedings
- booktitle
- ISSCC
- year
- 2024
- pages
- 192-194
- publisher
- IEEE
- crossref
- conf/isscc/2024
- ee
- https://doi.org/10.1109/ISSCC49657.2024.10454284
- isbn
- 979-8-3503-0620-0
- url
- http://dblp.uni-trier.de/db/conf/isscc/isscc2024.html#XuLKHZSLWXQMZFSO24
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%1 conf/isscc/XuLKHZSLWXQMZFSO24
%A Xu, Dingxin
%A Liu, Zezheng
%A Kuai, Yifeng
%A Huang, Hongye
%A Zhang, Yuncheng
%A Sun, Zheng
%A Liu, Bangan
%A Wang, Wenqian
%A Xiong, Yuang
%A Qiu, Junjun
%A Madany, Waleed
%A Zhang, Yi
%A Fadila, Ashbir Aviat
%A Shirane, Atsushi
%A Okada, Kenichi
%B ISSCC
%D 2024
%I IEEE
%K dblp
%P 192-194
%T 10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter.
%U http://dblp.uni-trier.de/db/conf/isscc/isscc2024.html#XuLKHZSLWXQMZFSO24
%@ 979-8-3503-0620-0
@inproceedings{conf/isscc/XuLKHZSLWXQMZFSO24,
added-at = {2024-03-19T00:00:00.000+0100},
author = {Xu, Dingxin and Liu, Zezheng and Kuai, Yifeng and Huang, Hongye and Zhang, Yuncheng and Sun, Zheng and Liu, Bangan and Wang, Wenqian and Xiong, Yuang and Qiu, Junjun and Madany, Waleed and Zhang, Yi and Fadila, Ashbir Aviat and Shirane, Atsushi and Okada, Kenichi},
biburl = {https://www.bibsonomy.org/bibtex/2dd7cb528b618829460098335f1d080f4/dblp},
booktitle = {ISSCC},
crossref = {conf/isscc/2024},
ee = {https://doi.org/10.1109/ISSCC49657.2024.10454284},
interhash = {5796abb787f724cf14f567c57a885809},
intrahash = {dd7cb528b618829460098335f1d080f4},
isbn = {979-8-3503-0620-0},
keywords = {dblp},
pages = {192-194},
publisher = {IEEE},
timestamp = {2024-04-09T20:43:07.000+0200},
title = {10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter.},
url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2024.html#XuLKHZSLWXQMZFSO24},
year = 2024
}