%0 Journal Article %1 journals/jssc/ZanchiT05 %A Zanchi, Alfio %A Tsay, Frank (Ching-Yuh) %D 2005 %J IEEE J. Solid State Circuits %K dblp %N 6 %P 1225-1237 %T A 16-bit 65-MS/s 3.3-V pipeline ADC core in SiGe BiCMOS with 78-dB SNR and 180-fs jitter. %U http://dblp.uni-trier.de/db/journals/jssc/jssc40.html#ZanchiT05 %V 40

@article{journals/jssc/ZanchiT05, added-at = {2022-03-02T00:00:00.000+0100}, author = {Zanchi, Alfio and Tsay, Frank (Ching-Yuh)}, biburl = {https://www.bibsonomy.org/bibtex/23c8d740b0fe9ad4024a7b7473b354e68/dblp}, ee = {https://doi.org/10.1109/JSSC.2005.848020}, interhash = {5cda5573f3931d169e9a9601663f119d}, intrahash = {3c8d740b0fe9ad4024a7b7473b354e68}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 6, pages = {1225-1237}, timestamp = {2024-04-08T10:42:26.000+0200}, title = {A 16-bit 65-MS/s 3.3-V pipeline ADC core in SiGe BiCMOS with 78-dB SNR and 180-fs jitter.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc40.html#ZanchiT05}, volume = 40, year = 2005 }