%0 Conference Paper %1 conf/fpga/WirthlinKMRLD16 %A Wirthlin, Michael J. %A Keller, Andrew M. %A McCloskey, Chase %A Ridd, Parker %A Lee, David %A Draper, Jeffrey %B FPGA %D 2016 %E Chen, Deming %E Greene, Jonathan W. %I ACM %K dblp %P 205-214 %T SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing. %U http://dblp.uni-trier.de/db/conf/fpga/fpga2016.html#WirthlinKMRLD16 %@ 978-1-4503-3856-1

@inproceedings{conf/fpga/WirthlinKMRLD16, added-at = {2018-11-06T00:00:00.000+0100}, author = {Wirthlin, Michael J. and Keller, Andrew M. and McCloskey, Chase and Ridd, Parker and Lee, David and Draper, Jeffrey}, biburl = {https://www.bibsonomy.org/bibtex/232c63709178a63a0fcd819b72670737c/dblp}, booktitle = {FPGA}, crossref = {conf/fpga/2016}, editor = {Chen, Deming and Greene, Jonathan W.}, ee = {https://doi.org/10.1145/2847263.2847278}, interhash = {5df9fb0d896c1673bf96b6952318e051}, intrahash = {32c63709178a63a0fcd819b72670737c}, isbn = {978-1-4503-3856-1}, keywords = {dblp}, pages = {205-214}, publisher = {ACM}, timestamp = {2018-11-07T12:47:21.000+0100}, title = {SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing.}, url = {http://dblp.uni-trier.de/db/conf/fpga/fpga2016.html#WirthlinKMRLD16}, year = 2016 }