%0 Generic %1 agourivdeshpande2013diagnostic %A A. Gouri V Deshpande, B. Abhijit Gadad %A Kumar, C. Dr. Priyatam %B 2013 Information Technology and Power Electronics %D 2013 %E R.Rajesh, Dr. %I ACEEE (A Computer division of IDES) %K (AHB) AMBA Communication protocols %T Diagnostic Access of AMBA-AHB Communication Protocols %U http://searchdl.org/public/book_series/LSCS/6/515.pdf %X In this paper a diagnostic access of AMBA AHB communication protocols is designed and implemented. AMBA AHB communication protocols are designed using master slave topology. A core is designed for implementation of communication protocols between master and slave device to perform efficient write operation. The process involves design and implementation of a master unit and a slave unit. Further a test bench is designed to simulate the communication between master and slave. A synthesis report of the process is generated using VHDL and XILINX. The process is configured for Address and Data bus of 32 bit width. The designed AMBA AHB communication protocol between master and single slave supports technology independent data transfer between high band width and high clock frequency multiprocessors and multi-CPU based embedded systems like arm processors and low bandwidth peripherals like IC based processors, standard macro cells, flash memory etc. The features required for high performance, high clock frequency systems including burst transfers, single clock edge operations, non–tristate implementation and wider data bus configuration are implemented in the design.

@conference{agourivdeshpande2013diagnostic, abstract = {In this paper a diagnostic access of AMBA AHB communication protocols is designed and implemented. AMBA AHB communication protocols are designed using master slave topology. A core is designed for implementation of communication protocols between master and slave device to perform efficient write operation. The process involves design and implementation of a master unit and a slave unit. Further a test bench is designed to simulate the communication between master and slave. A synthesis report of the process is generated using VHDL and XILINX. The process is configured for Address and Data bus of 32 bit width. The designed AMBA AHB communication protocol between master and single slave supports technology independent data transfer between high band width and high clock frequency multiprocessors and multi-CPU based embedded systems like arm processors and low bandwidth peripherals like IC based processors, standard macro cells, flash memory etc. The features required for high performance, high clock frequency systems including burst transfers, single clock edge operations, non–tristate implementation and wider data bus configuration are implemented in the design.}, added-at = {2014-02-04T09:52:08.000+0100}, author = {A. Gouri V Deshpande, B. Abhijit Gadad and Kumar, C. Dr. Priyatam}, biburl = {https://www.bibsonomy.org/bibtex/29460af7a6f48ae928538f5fc79a3b1b9/idescitation}, booktitle = {2013 Information Technology and Power Electronics}, editor = {R.Rajesh, Dr.}, interhash = {5e93c52c54650c91969b40a7a1193a66}, intrahash = {9460af7a6f48ae928538f5fc79a3b1b9}, keywords = {(AHB) AMBA Communication protocols}, organization = {Institute of Doctors Engineers and Scientists}, publisher = {ACEEE (A Computer division of IDES)}, timestamp = {2014-02-04T09:52:08.000+0100}, title = {Diagnostic Access of AMBA-AHB Communication Protocols}, url = {http://searchdl.org/public/book_series/LSCS/6/515.pdf}, year = 2013 }