%0 Journal Article %1 journals/tcad/RavishankarAK12 %A Ravishankar, Chirag %A Anderson, Jason Helge %A Kennings, Andrew A. %D 2012 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 9 %P 1305-1318 %T FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture. %U http://dblp.uni-trier.de/db/journals/tcad/tcad31.html#RavishankarAK12 %V 31

@article{journals/tcad/RavishankarAK12, added-at = {2020-09-24T00:00:00.000+0200}, author = {Ravishankar, Chirag and Anderson, Jason Helge and Kennings, Andrew A.}, biburl = {https://www.bibsonomy.org/bibtex/23821f2ac50f032c8e60933c8040c039e/dblp}, ee = {https://doi.org/10.1109/TCAD.2012.2192478}, interhash = {6256298350a1bbe65780e918269c8935}, intrahash = {3821f2ac50f032c8e60933c8040c039e}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 9, pages = {1305-1318}, timestamp = {2020-09-25T11:45:41.000+0200}, title = {FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad31.html#RavishankarAK12}, volume = 31, year = 2012 }