%0 Conference Paper %1 conf/fpl/VeredasP06 %A Veredas, Francisco-Javier %A Pfleiderer, Hans-Jörg %B FPL %D 2006 %I IEEE %K dblp %P 1-2 %T Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2006.html#VeredasP06 %@ 1-4244-0312-X

@inproceedings{conf/fpl/VeredasP06, added-at = {2017-05-21T00:00:00.000+0200}, author = {Veredas, Francisco-Javier and Pfleiderer, Hans-Jörg}, biburl = {https://www.bibsonomy.org/bibtex/21ced1e872e990fd61c41d4b8b6065b67/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2006}, ee = {https://doi.org/10.1109/FPL.2006.311358}, interhash = {63e2659aefa6ea271c25072add1c3be6}, intrahash = {1ced1e872e990fd61c41d4b8b6065b67}, isbn = {1-4244-0312-X}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2019-10-17T19:14:15.000+0200}, title = {Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2006.html#VeredasP06}, year = 2006 }