%0 Journal Article %1 journals/tvlsi/BajwaHKGNSSS97 %A Bajwa, Raminder Singh %A Hiraki, Mitsuru %A Kojima, Hirotsugu %A Gorny, Douglas J. %A ichi Nitta, Ken %A Shridhar, Avadhani %A Seki, Koichi %A Sasaki, Katsuro %D 1997 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 4 %P 417-424 %T Instruction buffering to reduce power in processors for signal processing. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi5.html#BajwaHKGNSSS97 %V 5

@article{journals/tvlsi/BajwaHKGNSSS97, added-at = {2020-03-11T00:00:00.000+0100}, author = {Bajwa, Raminder Singh and Hiraki, Mitsuru and Kojima, Hirotsugu and Gorny, Douglas J. and ichi Nitta, Ken and Shridhar, Avadhani and Seki, Koichi and Sasaki, Katsuro}, biburl = {https://www.bibsonomy.org/bibtex/287e1fad5f8278bcaa53b6c9545de553d/dblp}, ee = {https://doi.org/10.1109/92.645068}, interhash = {67962d42813e60aa81507155e0b1a196}, intrahash = {87e1fad5f8278bcaa53b6c9545de553d}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 4, pages = {417-424}, timestamp = {2020-03-12T11:41:56.000+0100}, title = {Instruction buffering to reduce power in processors for signal processing.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi5.html#BajwaHKGNSSS97}, volume = 5, year = 1997 }