%0 Conference Paper %1 conf/aspdac/LiuLC10 %A Liu, Wen-Hao %A Li, Yih-Lang %A Chen, Hui-Chi %B ASP-DAC %D 2010 %I IEEE %K dblp %P 389-394 %T Minimizing clock latency range in robust clock tree synthesis. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2010.html#LiuLC10 %@ 978-1-60558-837-7

@inproceedings{conf/aspdac/LiuLC10, added-at = {2024-08-09T00:00:00.000+0200}, author = {Liu, Wen-Hao and Li, Yih-Lang and Chen, Hui-Chi}, biburl = {https://www.bibsonomy.org/bibtex/26fbb06701691a5f934d0f7594ee610c9/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2010}, ee = {http://dl.acm.org/citation.cfm?id=1899817}, interhash = {69b0db2b1564ae14c582c784f2d0a45a}, intrahash = {6fbb06701691a5f934d0f7594ee610c9}, isbn = {978-1-60558-837-7}, keywords = {dblp}, pages = {389-394}, publisher = {IEEE}, timestamp = {2024-08-12T07:29:06.000+0200}, title = {Minimizing clock latency range in robust clock tree synthesis.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2010.html#LiuLC10}, year = 2010 }